EE2020 Digital Fundamentals

AY2017/2018 Semester 1
Faculty of Engineering
National University of Singapore

Project

• Use Midicsv.exe to convert a .mid music file format to a .csv file containing human-readable information about the music.
• Use midi_note_frequency_coe_generator.js to generate the .coe file used by Verilog program to decide the frequency of all MIDI notes.

Module Description

This is a first course that introduces fundamental digital logic, digital circuits, and programmable devices. The course also provides an overview of computer systems. This course provides students with an understanding of the building blocks of modern digital systems and methods of designing, simulating and realizing such systems. The emphasis of this module is on understanding the fundamentals of digital design across different levels of abstraction using hardware description languages.

Modular Credit

5

Weekly Workload

• Lecture: 3 hrs
• Tutorial: 1 hrs
• Lab: 2 hrs
• Project: 2 hrs
• Preparation: 4 hrs

Final Quiz Date

15-11-2017 10:00 AM

CA Components

• Labs
• Project
• Midterm Quiz
• Final Quiz

Licence

• GNU General Public Licence 3.0